1. Field of the Invention
The present general inventive concept is related to circuit design apparatuses and circuit design methodologies of circuit designs formed of physically divided sub-circuits. More specifically, the present general inventive concept affords a circuit designer with design tools to rapidly configure and analyze variants of a circuit design created by moving one or more selected circuit elements represented in a user interface across a boundary separating sub-circuits of the circuit design.
2. Description of the Related Art
As design trends of electronic circuits tend toward more compact circuitry, circuit designers rely more heavily on separating large, complex circuits into separate domains, such as through separations of functionality or fabrication process. For example, although various radio-frequency (RF) circuit designs can be physically implemented as a System-on-Chip (SoC), whereby the entire circuit is formed on a single circuit-bearing medium such as silicon, certain performance criteria require many RF circuit designs to be implemented as a System-in-Package (SiP), whereby various sub-circuits are respectively realized on separate circuit-bearing media. While the SoC implementation incorporates the necessary passive components on the circuit-bearing medium itself, typically on a silicon die, such implementations are also very costly and are characterized by a low quality-factor (Q). Alternatively, the circuit may be implemented as a SiP to separate the passive components from the silicon die, and, instead, the passive components are integrated on an inexpensive and high quality package substrate. However, separating the passive components in this manner comes with a whole new set of challenges and disadvantages, such as, for example, performance degradation due to parasitic effects from the packaging interfaces between the passive components and the circuit on the silicon die, reduction in yield due to relatively large process variations in packaging as compared with integrated circuit technology, and counteracting any savings of chip area achieved by relocating the passive components from the die by the addition of extra input/output (I/O) pads on the silicon die to connect with the exterior passive components.
Design decisions as to whether passive components should be constructed on a circuit-bearing medium separate from the die, referred to as off-chip, or fabricated on the silicon die, or on-chip, are typically made based on analysis of several important metrics, such as cost and performance (gain, noise and linearity) of the resulting system and ability of the design to tolerate fabrication process variations. Such analysis can be performed through simulation of modeled variants of the RF-SiP design, where such variants are created by changing the placement of passive components in the design environment, and evaluating the performance of the corresponding circuit model. The change in component placement may be localized within the die itself or within the off-chip substrate itself, or across die and off-chip substrate, or across dies within the SiP design. Whereas it is quite intuitive and thus easy for a designer to choose the placement of a high value passive component as off-chip and common value passive component as on-chip, the same is neither intuitive nor easy when the passive component has neither a common value nor a high value.
The conventional approach to construct RF-SiP design variants and analyze their respective performances involves a large number of manual steps in not only the SiP/IC design flow, but in the simulation flow as well. Consequently, the process of creating and analyzing even a small number of circuit variants is not only very time consuming, but prone to error. Moreover, the number of manual operations to create and analyze circuit variants increases with the number of passive components being considered for the on-chip vs. off-chip trade-off. Any unsatisfactory performance of a SiP variant would cause the designer to repeat all of the previously performed steps: changing SiP and IC die schematics to create variants, generating a floor-plan and estimating silicon area for each die variant, generating the die footprint to be used in the off-chip substrate layout for each variant, generating the floor-plan for each off-chip circuit variant, extracting the relevant portion of the design impacted by way of moving the component to simulate the performance of the circuit responsive to the move, and performing tradeoff analysis by comparing the simulation results of the variants.
FIG. 1 illustrates basic steps to move a passive component across a boundary of a die circuit and an external off-chip substrate, and to perform the subsequent analysis on the resulting variant. In summary, the operations illustrated in the flow diagram of FIG. 1 include: editing the schematic of the die circuit to delete or add the passive component, changing the die interfaces accordingly, generating/updating the die floor-plan based on the edited schematic to determine die placement and to estimate the required area, creating the die footprint and die symbol, e.g., using the updated die boundary and interface information to create the die footprint and symbol to be used in off-chip design, editing the off-chip schematic to add or delete the passive component, deleting the original die symbol and adding the newly created symbol, updating the connectivity using the new interface, generating/updating the off-chip floor-plan from the off-chip schematic, extracting the portion of the circuit design that tests the efficacy of moving the component, manually creating a new schematic for the critical portion of the design by performing trial simulations to ensure all related components are copied into the test model, creating a simulation netlist for the off-chip design, ensuring the model binding is to the correct fabrication technology, inserting the parasitic models of the die interface and passive component connections into the off-chip netlist based on placement and stack-up, simulating and analyzing the variant test-bench, and repeating the foregoing operations for every move of a candidate component from off-chip to on-chip, and vice-versa, until a decision is made.
As is apparent from the flow diagram of FIG. 1, the large number of steps and overall complexity of performing conventional trade-off analysis renders the entire process unmanageable, inefficient, and costly. The large number of steps to create a variant restricts the designer to attempt only a limited number of combinations, thereby resulting in non-optimal and inefficient trade-off analysis.
In the absence of sufficient tools to assist in rapid quantitative analysis of the performance of the circuit, RF circuit designers often have difficulty in making a choice with respect to the placement of the passive components in an RF design. These illustrative RF design difficulties are in fact indicative of shortcomings in the much broader field of general circuit design and analysis, namely creating and analyzing circuit variants in a seamless manner. Accordingly, there is an apparent need for a unified system and method that allows easy and rapid performance analysis of variants of circuits formed from components that can be distributed across more than one circuit-bearing medium.